 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DUAL POLARISATION SWITCH TWIN LNB MULTIPLEX CONTROLLER ISSUE 1- JANUARY 2001 DEVICE DESCRIPTION The ZLNB101 dual polarisation switch controller is one of a wide range of satellite receiver LNB support circuits. It features two completely independent channels, each providing two logic outputs under the control of a voltage sensitive input. It is intended for use in Twin LNB designs, replacing many dIscrete components to save both manufacturing cost and PCB size whilst improving reliability. The two inputs of the ZLNB101 have a nominal threshold of 14.5V. Their threshold is temperature compensated to minimise drift. Each features a low and stable input current that enables transient protection to be achieved with the addition of only a single resistor per channel. Normal and an inverted outputs are provided for each input. All outputs can source 15mA and sink 10mA making them suitable to drive TTL and CMOS logic, pin diodes and for IF-amp supply switching. ZLNB101 The ZLNB101 operates from a single supply of between 5-12V. Its quiescent current is typically only 4mA and this does not change significantly with load or logic state. It is available in either the standard SO8 or space saving MSOP8 surface mount packages. Device operating temperature is -40C to +85C to suit a wide range of environmental conditions. FEATURES APPLICATIONS * * * * * * * * * provides polarity detection and control transient resistant low input current low supply current temperature compensated input threshold standard and inverted output available simultaneously wide supply operating range dual polarisation switch eliminates external components simplifies design * * * twin LNBs IF switch box LNB switch boxes 75 78 ZLNB101 ABSOLUTE MAXIMUM RATINGS Supply Voltage Supply Current VPOL1 and VPOL2 Input Voltage Operating Temperature Storage Temperature -0.6V to 15V 50mA 25V Continuous -40 to 85C -40 to 85 Power Dissipation (Tamb= 25C) SO8 500mW MSOP8 500mW ELECTRICAL CHARACTERISTICS TEST CONDITIONS (Unless otherwise stated): Tamb= 25C,VCC=5V,ID=10mA (RCAL1 =33k) SYMBOL PARAMETER VCC ICC Supply Voltage Supply Current All inputs and outputs open circuit IVERT1 = IVERT2 = 10mA, VPOL1 = VPOL2 = 14V IHOR1 = IHOR2 = 10mA, VPOL1 = VPOL2 = 15.0V VPOL1 = VPOL2 = 25V (Note 4) (Note 1) (Note 4) 10 14.0 20 14.5 CONDITIONS Min 5 LIMITS Typ Max 12 10 30 30 40 15.0 100 s V mA mA mA A UNITS VPOL1 and VPOL2 Inputs IPOL VTPOL TSPOL VVHIGH VVHIGH VVHIGH VVLOW Current Threshold Voltage Switching Speed Vert 1/2 Outputs I VERT1 =I VERT2 =10mA, Voltage High V POL1 = V POL2 = 14V I VERT1 =I VERT2 =15mA, Voltage High V POL1 = V POL2 = 14V Voltage High I VERT1 =I VERT2 =10A, V POL1 = V POL2 = 14V Voltage Low I VERT1 =I VERT2=-10mA, V POL1 = V POL2 = 15.0V Hor 1/2 Outputs Voltage High Voltage High Voltage High Voltage Low I HOR1 =I HOR2=10mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=15mA, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=10A, V POL1 = V POL2 = 15.0V I HOR1=I HOR2=-10mA, V POL1 = V POL2 = 14V VCC-1.0 VCC-0.8 VCC VCC-1.2 VCC-0.9 VCC VCC-0.2 VCC-0.1 VCC 0 0.25 0.5 V V V V VVHIGH VVHIGH VVHIGH VVLOW VCC-1.0 VCC-0.8 VCC VCC-1.2 VCC-0.9 VCC VCC-0.2 VCC-0.1 VCC 0 0.25 0.5 V V V V 76 78 ZLNB101 Note:1) VPOL1 and VPOL2 switching thresholds apply over the whole operating temperature range specified above. 2) Inputs VPOL1 and VPOL2 are designed to be wired to the power input of an LNB via high value (10k) resistors. Input VPOL1 controls outputs Vert1 and Hor1. Input VPOL2 controls outputs Vert2 and Hor2. With either input voltage set at or below 14V, the corresponding Vert pin will be high and Hor pin low. With either input voltage at or above 15.0V, the corresponding Vert pin will be low and Hor pin high. Any input or output not required may be left open-circuit. 3) All outputs are designed to be compatible with TTL, CMOS, pin diode and IF Amp loads. 4) Applied via 10k resistors The following block diagram shows a typical block diagram twin LNB design. The ZLNB101 provides the two polarity switches required to decode the two independent receiver feeds. Additionally the front end bias requirements of the LNB are provided by the ZNBG4000 or ZNBG6000 offering a very efficient and cost effective solution. Horizontal Gain Stage GaAs/HEMTFET Antenna Mixer Control Input <=14V-Horizontal >=15V-Vertical DC Input 13-25V 1 3 + Horizontal H/V Output 1 Bias Generator ZNBG40XX Series ZLNB101 Series Control Dual H/V Switch PIN Diode MUX IF down feed 950-1750 MHz - Standard Band 950-2050 MHz - Enhanced Band 2 4 + Mixer Vertical H/V Output 2 Vertical Antenna Gain Stage GaAs/HEMTFET 77 78 ZLNB101 CONNECTION DIAGRAMS Part Number ORDERING INFORMATION Package MSOP8 SO8 Part Mark ZLNB101 ZLNB101 Vert2 Hor2 Gnd Vp2 1 2 3 4 8 7 6 5 Hor1 Vert1 Vcc Vp1 ZLNB101X8 ZLNB101N8 MSOP8 Vert1 Hor1 Vert2 Hor2 1 2 3 4 8 7 6 5 Vcc Vp1 Vp2 Gnd SO8 78 78 ZLNB101 PACKAGE DIMENSIONS MSOP8 D DIM A A1 B C D e e1 E H L Millimetres MIN 0.91 0.10 0.25 0.13 2.95 0.65 0.33 2.95 4.78 0.41 0 MAX 1.11 0.20 0.36 0.18 3.05 NOM NOM 3.05 5.03 0.66 6 Inches MIN 0.036 0.004 0.010 0.005 0.116 0.0256 0.0128 0.116 0.188 0.016 0 MAX 0.044 E 87 65 0.008 0.014 0.007 0.120 NOM 0.120 0.198 0.026 6 A eX6 1 2 34 H NOM B C L A1 SO8 DIM A B C D E F G J K L Millimetres Min 4.80 1.27 BSC 0.53 REF 0.36 3.81 1.35 0.10 5.80 0 0.41 0.46 3.99 1.75 0.25 6.20 8 1.27 Max 4.98 Inches Min 0.189 0.05 BSC 0.02 REF 0.014 0.15 0.05 0.004 0.23 0 0.016 0.018 0.157 0.07 0.010 0.24 8 0.050 Max 0.196 79 78 |
Price & Availability of ZLNB101
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |